[PATCH] D78764: [RISCV] Update debug scratch register names
Pengxuan Zheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 4 09:05:21 PDT 2020
pzheng updated this revision to Diff 261839.
pzheng added a comment.
Address @asb's comments
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D78764/new/
https://reviews.llvm.org/D78764
Files:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/RISCVSystemOperands.td
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
llvm/test/MC/RISCV/machine-csr-names.s
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D78764.261839.patch
Type: text/x-patch
Size: 4336 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200504/b7328541/attachment.bin>
More information about the llvm-commits
mailing list