[PATCH] D79193: [AArch64][SVE] Implement lowering for SIGN_EXTEND etc. of SVE predicates.
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 1 21:36:39 PDT 2020
efriedma marked an inline comment as done.
efriedma added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:998-999
return MVT::i32;
+ if (VT.isScalableVector())
+ return EVT::getVectorVT(C, MVT::i1, VT.getVectorElementCount());
return VT.changeVectorElementTypeToInteger();
----------------
fpetrogalli wrote:
> I am not sure if it is possible, but is this change tested anywhere?
sve-fcmp.ll fails without this change.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D79193/new/
https://reviews.llvm.org/D79193
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