[PATCH] D79193: [AArch64][SVE] Implement lowering for SIGN_EXTEND etc. of SVE predicates.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:998-999
     return MVT::i32;
+  if (VT.isScalableVector())
+    return EVT::getVectorVT(C, MVT::i1, VT.getVectorElementCount());
   return VT.changeVectorElementTypeToInteger();
----------------
I am not sure if it is possible, but is this change tested anywhere?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79193/new/

https://reviews.llvm.org/D79193