[PATCH] D79268: [RISCV] Implement Hooks to avoid chaining SELECT

[Sam Elliott via Phabricator via llvm-commits]

lenary updated this revision to Diff 261569.
lenary added a comment.

@luismarques pointed out there's an easier implementation of this: to use
`setHasMultipleConditionRegisters`, instead of overriding
`shouldNormalizeToSelectSequence`. This is correct as RISC-V branches can use
any register they want.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79268/new/

https://reviews.llvm.org/D79268

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/select-or.ll
  llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll

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