[PATCH] D79268: [RISCV] Implement Hooks to avoid chaining SELECT

Sam Elliott via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri May 1 17:17:41 PDT 2020


lenary created this revision.
lenary added a reviewer: luismarques.
Herald added subscribers: llvm-commits, evandro, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
Herald added a project: LLVM.
lenary added a parent revision: D79267: [RISCV][NFC] Add Test for (select (or B1, B2), X, Y).
lenary updated this revision to Diff 261569.
lenary added a comment.

@luismarques pointed out there's an easier implementation of this: to use
`setHasMultipleConditionRegisters`, instead of overriding
`shouldNormalizeToSelectSequence`. This is correct as RISC-V branches can use
any register they want.


This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V
will lower SELECTs into control flow, which is not a great idea.

The first hook, `shouldNormalizeToSelectSequence`, turns off the following
DAGCombiner folds:

  select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y)
  select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y)

This has the effect of ensuring more logic is done before fewer jumps.

The second hook `setJumpIsExpensive` controls a flag that has a similar purpose
and is used in CodeGenPrepare and the SelectionDAGBuilder.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79268

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/select-or.ll
  llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll

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