[PATCH] D78994: [Target][ARM] Add a fix for an LSR Pattern that can't be tail-predicated

Pierre van Houtryve via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri May 1 00:05:19 PDT 2020


Pierre-vh marked an inline comment as done.
Pierre-vh added inline comments.


================
Comment at: llvm/lib/Target/ARM/MVETailPredication.cpp:326
 
+  FixLSRPattern(L, *SE);
+
----------------
samparker wrote:
> Pierre-vh wrote:
> > samparker wrote:
> > > We haven't even inserted the VCTP yet! Your test shouldn't contain the intrinsic. If TryConvert returns the VCTP, then you could use it directly and not have to iterate through the loop doing your add search.
> > I think this pattern (generated by LSR) can only happen when there is a VCTP intrinsic already present. 
> > 
> > The reproducer I had was using it, and I can't think of a way to trigger the same issue without the VCTP intrinsic. 
> > Also, if I were to implement this by using the result of TryConvert, it wouldn't fix the original issue as it wouldn't catch existing VCTP intrinsics.
> > 
> > I should make this clearer in the patch, or perhaps this fix is just misplaced? (Not in the right pass?)
> > What do you think?
> Ah okay, then yes, this is not the right place to fix this issue. I think it makes sense to do it in ARMLowOverheadLoops before we decide that we can't do tail predication.
It looks like fixing it there will be a bit harder.

The MIR going into ARMLowOverheadLoops looks like this:
```
  renamable $r0, dead $cpsr = nsw tADDi3 renamable $r1, 2, 14, $noreg
  ; ...
  renamable $lr = nuw nsw t2ADDrs renamable $r9, killed renamable $r1, 19, 14, $noreg, $noreg
  ; ...
  t2DoLoopStart renamable $lr
bb.3 (%ir-block.51, align 2):
  ; ...
  renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0(tied-def 0), 4, 14, $noreg
  ; ...
  renamable $vpr = MVE_VCTP32 renamable $r0, 0, $noreg
```

I'd need to prove that `$r0` == `$lr` to remove the `$r0` definitions and replace the uses with `$lr`. I don't know how challenging that is?
I can try to do it if you want, but I think it's easier to do this in an IR pass because the pattern is easier to find and rewrite there.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78994/new/

https://reviews.llvm.org/D78994





More information about the llvm-commits mailing list