[PATCH] D78994: [Target][ARM] Add a fix for an LSR Pattern that can't be tail-predicated

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 30 11:15:11 PDT 2020


dmgreen added inline comments.


================
Comment at: llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tp-lsr-patterns.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -mve-tail-predication -disable-mve-tail-predication=false %s -S -o - | FileCheck %s
+
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I think that if we have what is essentially a phase-ordering problem between two passes in the backend, it's worth running an llc test to check the whole thing.

Bonus points for adding the test before and just showing the diffs in the patch. 


================
Comment at: llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tp-lsr-patterns.ll:90
+
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="all" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-dotprod,-fp16fml,-hwdiv-arm,-sb,-sha2" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
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This test can probably be cleaned up a bit too? These attribute are often unnecessary if you get the args correct.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D78994/new/

https://reviews.llvm.org/D78994





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