[PATCH] D79096: [SelectionDAG] Unify scalarizeVectorLoad and VectorLegalizer::ExpandLoad

Thu Apr 30 14:00:27 PDT 2020

craig.topper added inline comments.

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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:6620
+      SDValue Elt =
+          DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask);
+      SDValue Scalar = DAG.getNode(ISD::TRUNCATE, SL, SrcEltVT, Elt);
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LemonBoy wrote:
> craig.topper wrote:
> > LemonBoy wrote:
> > > craig.topper wrote:
> > > > Why do we need to AND before the TRUNCATE? Isn't the AND masking to the same number of bits as the truncate?
> > > I found that sometimes the generated pattern would be something like `(anyext DstEltVT (truncate SrcEltVT (load LoadVT))` so when the optimizer kicks in and folds the `truncate` and `anyext` only the load remains.
> > Why is that bad?
> The extra bits are never masked away. If you bypass the `AND` and check out the generated code for `test2` in `X86/pr15267.ll` you can see the packed `4i1` is only shifted and never and-ed so the generated vector has garbage in upper bits.
Its ok that they are garbage. Type legalization inserted the anyextend which allowed them to be garbage. Type legalization in the caller that consumes the vector result is responsible for clearing them if it needs to.

Repository:
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  https://reviews.llvm.org/D79096/new/

https://reviews.llvm.org/D79096