[PATCH] D79078: [VectorCombine] Leave reduction operation to SLP

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

This needs a phase-ordering test.
Why shouldn't SLPVectorizer be taught about that pattern instead?



================
Comment at: llvm/test/Transforms/VectorCombine/X86/extract-binop.ll:492
+
+define i32 @ext_ext_reduction(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: @ext_ext_reduction(
----------------
Which is now being transformed into 
```
define i32 @ext_ext_reduction(<4 x i32> %x, <4 x i32> %y) {
  %and = and <4 x i32> %x, %y
  %1 = shufflevector <4 x i32> %and, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
  %2 = or <4 x i32> %1, %and
  %3 = extractelement <4 x i32> %2, i64 0
  %vecext.2 = extractelement <4 x i32> %and, i32 2
  %add.2 = or i32 %vecext.2, %3
  %vecext.3 = extractelement <4 x i32> %and, i32 3
  %add.3 = or i32 %vecext.3, %add.2
  ret i32 %add.3
}
```



Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D79078/new/

https://reviews.llvm.org/D79078