[PATCH] D78772: [AMDGPU] Adapt GCNRegBankReassign for 16 bit subregs

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec marked an inline comment as done.
rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp:463
+  if (Size == 16)
+    return AMDGPU::SGPR_LO16RegClass.contains(PhysReg);
+
----------------
arsenm wrote:
> Does this need to be updated for SReg_Lo16 in the other patch?
No, pass does not reassign special SGPRs. In essence you cannot replace vcc with s[0:1] here.


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  https://reviews.llvm.org/D78772/new/

https://reviews.llvm.org/D78772