[PATCH] D78772: [AMDGPU] Adapt GCNRegBankReassign for 16 bit subregs
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 28 12:56:45 PDT 2020
arsenm added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp:463
+ if (Size == 16)
+ return AMDGPU::SGPR_LO16RegClass.contains(PhysReg);
+
----------------
Does this need to be updated for SReg_Lo16 in the other patch?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D78772/new/
https://reviews.llvm.org/D78772
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