[llvm] 957c5dd - [PowerPC-QPX] add more test for QPX madd/msub operands order - NFC

[Chen Zheng via llvm-commits]

Author: Chen Zheng
Date: 2020-04-29T01:17:14-04:00
New Revision: 957c5dd78bc16df46eb2fb89044accaae18628fd

URL: https://github.com/llvm/llvm-project/commit/957c5dd78bc16df46eb2fb89044accaae18628fd
DIFF: https://github.com/llvm/llvm-project/commit/957c5dd78bc16df46eb2fb89044accaae18628fd.diff

LOG: [PowerPC-QPX] add more test for QPX madd/msub operands order - NFC

Added: 
    

Modified: 
    llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll b/llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll
index 99ae6d095d06..4c86a876a479 100644
--- a/llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll
+++ b/llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll
@@ -18,3 +18,62 @@ define <4 x float> @test_qvfmadds(<4 x float> %0, <4 x float> %1, <4 x float> %2
   %5 = fadd reassoc nsz <4 x float> %4, %0
   ret <4 x float> %5
 }
+
+define <2 x double> @test_qvfnmadd(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
+; CHECK: test_qvfnmadd
+; CHECK: QVFNMADD %2, %0, %1, implicit $rm
+;
+  %4 = fmul reassoc nsz <2 x double> %2, %1
+  %5 = fadd reassoc nsz <2 x double> %4, %0
+  %6 = fneg reassoc nsz <2 x double> %5
+  ret <2 x double> %6
+}
+
+define <4 x float> @test_qvfnmadds(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
+; CHECK: test_qvfnmadds
+; CHECK: QVFNMADDSs %2, %0, %1, implicit $rm
+;
+  %4 = fmul reassoc nsz <4 x float> %2, %1
+  %5 = fadd reassoc nsz <4 x float> %4, %0
+  %6 = fneg reassoc nsz <4 x float> %5
+  ret <4 x float> %6
+}
+
+define <2 x double> @test_qvfmsub(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
+; CHECK: test_qvfmsub
+; CHECK: QVFMSUB %2, %0, %1, implicit $rm
+;
+  %4 = fmul reassoc nsz <2 x double> %2, %1
+  %5 = fsub reassoc nsz <2 x double> %4, %0
+  ret <2 x double> %5
+}
+
+define <4 x float> @test_qvfmsubs(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
+; CHECK: test_qvfmsubs
+; CHECK: QVFMSUBSs %2, %0, %1, implicit $rm
+;
+  %4 = fmul reassoc nsz <4 x float> %2, %1
+  %5 = fsub reassoc nsz <4 x float> %4, %0
+  ret <4 x float> %5
+}
+
+define <2 x double> @test_qvfnmsub(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
+; CHECK: test_qvfnmsub
+; CHECK: QVFNMSUB %2, %0, %1, implicit $rm
+;
+  %4 = fmul reassoc nsz <2 x double> %2, %1
+  %5 = fsub reassoc nsz <2 x double> %4, %0
+  %6 = fneg reassoc nsz <2 x double> %5
+  ret <2 x double> %6
+}
+
+define <4 x float> @test_qvfnmsubs(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
+; CHECK: test_qvfnmsubs
+; CHECK: QVFNMSUBSs %2, %0, %1, implicit $rm
+;
+  %4 = fmul reassoc nsz <4 x float> %2, %1
+  %5 = fsub reassoc nsz <4 x float> %4, %0
+  %6 = fneg reassoc nsz <4 x float> %5
+  ret <4 x float> %6
+}
+