[PATCH] D78010: [CodeGen] Add new function unionImplicitOps() to union implicit register

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang marked 4 inline comments as done.
ZhangKang added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp:80-81
               // branch with a blr.
               BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()))
-                  .copyImplicitOps(*I);
+                  .unionImplicitOps(*I);
               MachineBasicBlock::iterator K = J--;
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arsenm wrote:
> Do you just want to setDesc here instead? It seems to me you expect the same implicit operands before and after in the test, and just want to change the opcode
In fact, I have another patch https://reviews.llvm.org/D76042 to use `setDesc()`. I have set the patch D76042 be `Change Planed`.  
In fact, if we use `setDesc()`, it means that we have assumed that the old instruction's implicit operands are same with the new instruction's.

If this patch can be approved, I will abandoned the patch D76042. I think use `unionImplicitOps `  is better， it doesn't assume that the old instruction's implicit operands are same with the new instruction's.


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Comment at: llvm/test/CodeGen/PowerPC/early-ret.mir:112
   ; CHECK:   renamable $cr0 = FCMPUS killed renamable $f1, killed renamable $f2
   ; CHECK:   BCLRn killed renamable $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
   ; CHECK: bb.2:
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lkail wrote:
> Is there any instruction define `$v2` between the last instruction of `bb.0.entry` and current one missing from check lines?
No, no instruction is missing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78010/new/

https://reviews.llvm.org/D78010