[llvm] 613f12d - [AArch64][GlobalISel] Set the current debug loc when missing in some cases.
David Blaikie via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 27 21:17:30 PDT 2020
Could you add more precise tests that validate the specific debug locations
that are present on the resulting instructions are the desired ones?
On Thu, Apr 23, 2020 at 1:36 AM Amara Emerson via llvm-commits <
llvm-commits at lists.llvm.org> wrote:
>
> Author: Amara Emerson
> Date: 2020-04-23T01:34:57-07:00
> New Revision: 613f12dd8e2403f5630ab299d2a1bb2cb111ead1
>
> URL:
> https://github.com/llvm/llvm-project/commit/613f12dd8e2403f5630ab299d2a1bb2cb111ead1
> DIFF:
> https://github.com/llvm/llvm-project/commit/613f12dd8e2403f5630ab299d2a1bb2cb111ead1.diff
>
> LOG: [AArch64][GlobalISel] Set the current debug loc when missing in some
> cases.
>
> Added:
>
>
> Modified:
> llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
> llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
>
> llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
> llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
> llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
>
> Removed:
>
>
>
>
> ################################################################################
> diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
> b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
> index 47c723cbf5a3..09e303eadd49 100644
> --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
> +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
> @@ -570,7 +570,7 @@ llvm::createMemLibcall(MachineIRBuilder &MIRBuilder,
> MachineRegisterInfo &MRI,
> }
> const char *Name = TLI.getLibcallName(RTLibcall);
>
> - MIRBuilder.setInstr(MI);
> + MIRBuilder.setInstrAndDebugLoc(MI);
>
> CallLowering::CallLoweringInfo Info;
> Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);
> @@ -3610,7 +3610,7 @@ LegalizerHelper::moreElementsVectorPhi(MachineInstr
> &MI, unsigned TypeIdx,
> LegalizerHelper::LegalizeResult
> LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
> LLT MoreTy) {
> - MIRBuilder.setInstr(MI);
> + MIRBuilder.setInstrAndDebugLoc(MI);
> unsigned Opc = MI.getOpcode();
> switch (Opc) {
> case TargetOpcode::G_IMPLICIT_DEF:
>
> diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
> b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
> index 60ccb3621a2e..cae5028f1925 100644
> --- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
> +++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp
> @@ -675,7 +675,7 @@ bool AArch64LegalizerInfo::legalizeShlAshrLshr(
> if (Amount > 31)
> return true; // This will have to remain a register variant.
> assert(MRI.getType(AmtReg).getSizeInBits() == 32);
> - MIRBuilder.setInstr(MI);
> + MIRBuilder.setInstrAndDebugLoc(MI);
> auto ExtCst = MIRBuilder.buildZExt(LLT::scalar(64), AmtReg);
> MI.getOperand(2).setReg(ExtCst.getReg(0));
> return true;
> @@ -704,7 +704,7 @@ bool AArch64LegalizerInfo::legalizeLoadStore(
> return false;
> }
>
> - MIRBuilder.setInstr(MI);
> + MIRBuilder.setInstrAndDebugLoc(MI);
> unsigned PtrSize = ValTy.getElementType().getSizeInBits();
> const LLT NewTy = LLT::vector(ValTy.getNumElements(), PtrSize);
> auto &MMO = **MI.memoperands_begin();
> @@ -722,7 +722,7 @@ bool AArch64LegalizerInfo::legalizeLoadStore(
> bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,
> MachineRegisterInfo &MRI,
> MachineIRBuilder &MIRBuilder)
> const {
> - MIRBuilder.setInstr(MI);
> + MIRBuilder.setInstrAndDebugLoc(MI);
> MachineFunction &MF = MIRBuilder.getMF();
> Align Alignment(MI.getOperand(2).getImm());
> Register Dst = MI.getOperand(0).getReg();
>
> diff --git
> a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
> b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
> index 6d50898117cd..5b32fd51f58c 100644
> ---
> a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
> +++
> b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
> @@ -1,5 +1,6 @@
> # NOTE: Assertions have been autogenerated by
> utils/update_mir_test_checks.py
> # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
> +# RUN: llc -O0 -debugify-and-strip-all-safe -march=aarch64
> -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
> --- |
> target datalayout =
> "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
> target triple = "aarch64"
>
> diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
> b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
> index 7ccb5166e4a7..dc42d603d737 100644
> --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
> +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
> @@ -1,5 +1,6 @@
> # NOTE: Assertions have been autogenerated by
> utils/update_mir_test_checks.py
> # RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
> +# RUN: llc -O0 -debugify-and-strip-all-safe -march=aarch64
> -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
> ---
> name: test_shift
> body: |
>
> diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
> b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
> index fe1d5a5002c9..7446fde7ba08 100644
> --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
> +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir
> @@ -1,5 +1,5 @@
> # NOTE: Assertions have been autogenerated by
> utils/update_mir_test_checks.py
> -# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s
> +# RUN: llc -O0 -run-pass=legalizer --debugify-and-strip-all-safe
> --debugify-level=locations %s -o - | FileCheck %s
>
> --- |
> target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
>
>
>
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