<div dir="ltr">Could you add more precise tests that validate the specific debug locations that are present on the resulting instructions are the desired ones?</div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Thu, Apr 23, 2020 at 1:36 AM Amara Emerson via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><br>
Author: Amara Emerson<br>
Date: 2020-04-23T01:34:57-07:00<br>
New Revision: 613f12dd8e2403f5630ab299d2a1bb2cb111ead1<br>
<br>
URL: <a href="https://github.com/llvm/llvm-project/commit/613f12dd8e2403f5630ab299d2a1bb2cb111ead1" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/613f12dd8e2403f5630ab299d2a1bb2cb111ead1</a><br>
DIFF: <a href="https://github.com/llvm/llvm-project/commit/613f12dd8e2403f5630ab299d2a1bb2cb111ead1.diff" rel="noreferrer" target="_blank">https://github.com/llvm/llvm-project/commit/613f12dd8e2403f5630ab299d2a1bb2cb111ead1.diff</a><br>
<br>
LOG: [AArch64][GlobalISel] Set the current debug loc when missing in some cases.<br>
<br>
Added: <br>
<br>
<br>
Modified: <br>
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp<br>
llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp<br>
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir<br>
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir<br>
llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir<br>
<br>
Removed: <br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp<br>
index 47c723cbf5a3..09e303eadd49 100644<br>
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp<br>
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp<br>
@@ -570,7 +570,7 @@ llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,<br>
}<br>
const char *Name = TLI.getLibcallName(RTLibcall);<br>
<br>
- MIRBuilder.setInstr(MI);<br>
+ MIRBuilder.setInstrAndDebugLoc(MI);<br>
<br>
CallLowering::CallLoweringInfo Info;<br>
Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);<br>
@@ -3610,7 +3610,7 @@ LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,<br>
LegalizerHelper::LegalizeResult<br>
LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,<br>
LLT MoreTy) {<br>
- MIRBuilder.setInstr(MI);<br>
+ MIRBuilder.setInstrAndDebugLoc(MI);<br>
unsigned Opc = MI.getOpcode();<br>
switch (Opc) {<br>
case TargetOpcode::G_IMPLICIT_DEF:<br>
<br>
diff --git a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp<br>
index 60ccb3621a2e..cae5028f1925 100644<br>
--- a/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp<br>
+++ b/llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp<br>
@@ -675,7 +675,7 @@ bool AArch64LegalizerInfo::legalizeShlAshrLshr(<br>
if (Amount > 31)<br>
return true; // This will have to remain a register variant.<br>
assert(MRI.getType(AmtReg).getSizeInBits() == 32);<br>
- MIRBuilder.setInstr(MI);<br>
+ MIRBuilder.setInstrAndDebugLoc(MI);<br>
auto ExtCst = MIRBuilder.buildZExt(LLT::scalar(64), AmtReg);<br>
MI.getOperand(2).setReg(ExtCst.getReg(0));<br>
return true;<br>
@@ -704,7 +704,7 @@ bool AArch64LegalizerInfo::legalizeLoadStore(<br>
return false;<br>
}<br>
<br>
- MIRBuilder.setInstr(MI);<br>
+ MIRBuilder.setInstrAndDebugLoc(MI);<br>
unsigned PtrSize = ValTy.getElementType().getSizeInBits();<br>
const LLT NewTy = LLT::vector(ValTy.getNumElements(), PtrSize);<br>
auto &MMO = **MI.memoperands_begin();<br>
@@ -722,7 +722,7 @@ bool AArch64LegalizerInfo::legalizeLoadStore(<br>
bool AArch64LegalizerInfo::legalizeVaArg(MachineInstr &MI,<br>
MachineRegisterInfo &MRI,<br>
MachineIRBuilder &MIRBuilder) const {<br>
- MIRBuilder.setInstr(MI);<br>
+ MIRBuilder.setInstrAndDebugLoc(MI);<br>
MachineFunction &MF = MIRBuilder.getMF();<br>
Align Alignment(MI.getOperand(2).getImm());<br>
Register Dst = MI.getOperand(0).getReg();<br>
<br>
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir<br>
index 6d50898117cd..5b32fd51f58c 100644<br>
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir<br>
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir<br>
@@ -1,5 +1,6 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
# RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s<br>
+# RUN: llc -O0 -debugify-and-strip-all-safe -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s<br>
--- |<br>
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"<br>
target triple = "aarch64"<br>
<br>
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir<br>
index 7ccb5166e4a7..dc42d603d737 100644<br>
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir<br>
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir<br>
@@ -1,5 +1,6 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
# RUN: llc -O0 -march=aarch64 -run-pass=legalizer %s -o - | FileCheck %s<br>
+# RUN: llc -O0 -debugify-and-strip-all-safe -march=aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s<br>
---<br>
name: test_shift<br>
body: |<br>
<br>
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir<br>
index fe1d5a5002c9..7446fde7ba08 100644<br>
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir<br>
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-vaarg.mir<br>
@@ -1,5 +1,5 @@<br>
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py<br>
-# RUN: llc -O0 -run-pass=legalizer %s -o - | FileCheck %s<br>
+# RUN: llc -O0 -run-pass=legalizer --debugify-and-strip-all-safe --debugify-level=locations %s -o - | FileCheck %s<br>
<br>
--- |<br>
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"<br>
<br>
<br>
<br>
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</blockquote></div>