[PATCH] D78829: [AMDGPU] Make SREG_LO16 legal
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 24 15:44:18 PDT 2020
arsenm added a comment.
Could we leave all instructions as 32-bit defs, but then have a 16-bit subreg copy as the only use?
%0:vgpr_32 = V_FOO_U16
%1:vgpr_16lo = COPY %0.sub16_lo
....
The register allocator would understand this and fold out the copy
================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp:315
+ if (MI->getOpcode() == AMDGPU::DELETED) {
+ if (isVerbose())
----------------
This is a red flag, this should never happen
================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:544-547
+ }
+
+ RC = RI.getPhysRegClass(DestReg);
+ }
----------------
We should make it so that MachineCopyPropagation can deal with this case
================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:545
+ }
+
+ RC = RI.getPhysRegClass(DestReg);
----------------
Why can't you just erase the instruction?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D78829/new/
https://reviews.llvm.org/D78829
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