[PATCH] D78829: [AMDGPU] Make SREG_LO16 legal
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 24 14:05:42 PDT 2020
rampitec created this revision.
rampitec added reviewers: arsenm, vpykhtin.
Herald added subscribers: kerbowa, asbirlea, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
rampitec added parent revisions: D78772: [AMDGPU] Adapt GCNRegBankReassign for 16 bit subregs, D78591: [AMDGPU] Define special SGPR subregs, D78597: [AMDGPU] Define AGPR subregs.
This includes a hack to fix illegal 32 to 16 bit copies.
The problem is when we make 16 bit subregs legal it creates
a huge amount of failures which can only be resolved at once
without a temporary hack like this.
The next step is to change operands, instruction definitions
and patterns until this hack is not needed.
There are also quite obvious regressions as seen in the tests,
but surprisingly not as huge as I expected.
I am not really sure it needs to be pushed right away, but
I definitely want to review it now and agree on the general
direction.
https://reviews.llvm.org/D78829
Files:
llvm/lib/Target/AMDGPU/AMDGPUMCInstLower.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/test/CodeGen/AMDGPU/bitreverse.ll
llvm/test/CodeGen/AMDGPU/bswap.ll
llvm/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll
llvm/test/CodeGen/AMDGPU/computeNumSignBits-mul.ll
llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
llvm/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll
llvm/test/CodeGen/AMDGPU/fshr.ll
llvm/test/CodeGen/AMDGPU/function-returns.ll
llvm/test/CodeGen/AMDGPU/idiv-licm.ll
llvm/test/CodeGen/AMDGPU/idot4u.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fcmp.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.icmp.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
llvm/test/CodeGen/AMDGPU/partial-shift-shrink.ll
llvm/test/CodeGen/AMDGPU/setcc-opt.ll
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