[PATCH] D77448: [PowerPC] Canonicalize shuffles to match more single-instruction masks on LE
Nemanja Ivanovic via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 24 14:05:47 PDT 2020
nemanjai marked an inline comment as done.
nemanjai added inline comments.
================
Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13850
+SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN,
+ SelectionDAG &DAG) const {
+ SDValue LHS = SVN->getOperand(0);
----------------
amyk wrote:
> I see that our other combine functions have an assert in the beginning checking the opcode. It might make sense to have one here checking `SVN->getOpcode() == ISD::VECTOR_SHUFFLE`?
The reason for the asserts in other combines is that they do not take a specialized node. This takes a `ShuffleVectorSDNode` pointer. It is not possible for a shuffle vector node to have an opcode other than vector shuffle.
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https://reviews.llvm.org/D77448/new/
https://reviews.llvm.org/D77448
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