[PATCH] D78764: [RISCV] Update debug scratch register names

Pengxuan Zheng via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Apr 24 12:26:44 PDT 2020


pzheng updated this revision to Diff 259956.
pzheng added a comment.

Moving debug mode registers to a new test file


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78764/new/

https://reviews.llvm.org/D78764

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
  llvm/test/MC/RISCV/debug-csr-names.s
  llvm/test/MC/RISCV/machine-csr-names.s

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