[llvm] 84584b0 - [SVE] Remove calls to isScalable from AARCH64

[Christopher Tetreault via llvm-commits]

Author: Christopher Tetreault
Date: 2020-04-23T13:09:17-07:00
New Revision: 84584b0d29a50cba325aa277cf84606dc2d2d123

URL: https://github.com/llvm/llvm-project/commit/84584b0d29a50cba325aa277cf84606dc2d2d123
DIFF: https://github.com/llvm/llvm-project/commit/84584b0d29a50cba325aa277cf84606dc2d2d123.diff

LOG: [SVE] Remove calls to isScalable from AARCH64

Reviewers: efriedma, sdesmalen, t.p.northover, mcrosier

Reviewed By: efriedma

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77758

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index ba31520d8837..992404c2687f 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -9728,7 +9728,7 @@ bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
     return false;
 
   // FIXME: Update this method to support scalable addressing modes.
-  if (Ty->isVectorTy() && cast<VectorType>(Ty)->isScalable())
+  if (isa<ScalableVectorType>(Ty))
     return AM.HasBaseReg && !AM.BaseOffs && !AM.Scale;
 
   // check reg + imm case: