[llvm] 479145a - [AMDGPU] Avoid hard-coded line numbers in error message checks

Jay Foad via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 23 13:06:34 PDT 2020 

Author: Jay Foad
Date: 2020-04-23T21:06:09+01:00
New Revision: 479145a5c2f2b71740599096750151f7bf0407db

URL: https://github.com/llvm/llvm-project/commit/479145a5c2f2b71740599096750151f7bf0407db
DIFF: https://github.com/llvm/llvm-project/commit/479145a5c2f2b71740599096750151f7bf0407db.diff

LOG: [AMDGPU] Avoid hard-coded line numbers in error message checks

This makes it easier for us to maintain downstream changes to some of
these tests. NFC.

Differential Revision: https://reviews.llvm.org/D78716

Added: 
    

Modified: 
    llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
    llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
    llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
    llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
    llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
    llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
    llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
    llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
index cfa5323497e7..312f7e378cb1 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
@@ -1,10 +1,9 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :7:27: incorrect register class for field
-# CHECK: scratchRSrcReg:  '$noreg'
 ---
 name: noreg_rsrc_reg
 machineFunctionInfo:
   scratchRSrcReg:  '$noreg'
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
 body:             |
   bb.0:
 

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
index f3da77e2dec8..5385b00db9c0 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
@@ -1,10 +1,9 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :7:21: unknown register name 'not_a_register_name'
-# CHECK: scratchRSrcReg:  '$not_a_register_name'
 ---
 name: invalid_rsrc_reg
 machineFunctionInfo:
   scratchRSrcReg:  '$not_a_register_name'
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: unknown register name 'not_a_register_name'
 body:             |
   bb.0:
 

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
index c66f6b62fa07..74f5d52b5f96 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
@@ -1,11 +1,10 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :8:27: incorrect register class for field
-# CHECK: frameOffsetReg:  '$vgpr0'
 
 ---
 name: wrong_reg_class_frame_offset_reg
 machineFunctionInfo:
   frameOffsetReg:  '$vgpr0'
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
 body:             |
   bb.0:
 

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
index 723f542f3361..91348ef19a5b 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
@@ -1,10 +1,9 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :7:21: expected a named register
-# CHECK: frameOffsetReg:  ''
 ---
 name: empty_frame_offset_reg
 machineFunctionInfo:
   frameOffsetReg:  ''
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
 body:             |
   bb.0:
 

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
index ee047b91aa4c..0e0666d1cdef 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
@@ -1,10 +1,9 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :7:21: expected a named register
-# CHECK: scratchRSrcReg:  ''
 ---
 name: empty_scratch_rsrc_reg
 machineFunctionInfo:
   scratchRSrcReg:  ''
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
 body:             |
   bb.0:
 

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
index e8164dabdd32..b0d62ac3f1f0 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
@@ -1,10 +1,9 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :7:24: expected a named register
-# CHECK: stackPtrOffsetReg:  ''
 ---
 name: empty_stack_ptr_offset_reg
 machineFunctionInfo:
   stackPtrOffsetReg:  ''
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: expected a named register
 body:             |
   bb.0:
 

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
index ac02af91a2db..3ecdde412e2d 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
@@ -1,11 +1,10 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :8:45: incorrect register class for field
-# CHECK: scratchRSrcReg:  '$vgpr0_vgpr1_vgpr2_vgpr3'
 
 ---
 name: wrong_reg_class_scratch_rsrc_reg
 machineFunctionInfo:
   scratchRSrcReg:  '$vgpr0_vgpr1_vgpr2_vgpr3'
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
 body:             |
   bb.0:
 

diff  --git a/llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir b/llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
index c15b0c6bc98b..47c7d281b393 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
@@ -1,11 +1,10 @@
 # RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
-# CHECK: :8:30: incorrect register class for field
-# CHECK: stackPtrOffsetReg:  '$vgpr0'
 
 ---
 name: wrong_reg_class_stack_ptr_offset_reg
 machineFunctionInfo:
   stackPtrOffsetReg:  '$vgpr0'
+# CHECK: :[[@LINE-1]]:{{[0-9]+}}: incorrect register class for field
 body:             |
   bb.0:

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