[PATCH] D78583: [RISCV] Add instruction definition for dret

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

Thanks for the patch, as we discussed last week I think supporting dret with the same ease as the privileged instructions is the right path. Given `dret` is defined in the debug spec rather than the privileged spec, could you please:

- Move the test to a new test file debug-valid.s
- Move the DRET instruction definition to a new section of RISCVInstrInfo.td with an internal header like

  //===----------------------------------------------------------------------===//
  // Debug instructions
  //===----------------------------------------------------------------------===//


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D78583/new/

https://reviews.llvm.org/D78583