[PATCH] D78583: [RISCV] Add instruction definition for dret

[Pengxuan Zheng via Phabricator via llvm-commits]

pzheng created this revision.
pzheng added reviewers: apazos, asb, lenary, luismarques.
Herald added subscribers: llvm-commits, evandro, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
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The instruction dret is used to return from debug mode and is defined in the
RISC-V debug mode spec.

https://github.com/riscv/riscv-opcodes/blob/master/opcodes-system


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78583

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/MC/RISCV/priv-valid.s


Index: llvm/test/MC/RISCV/priv-valid.s
===================================================================
--- llvm/test/MC/RISCV/priv-valid.s
+++ llvm/test/MC/RISCV/priv-valid.s
@@ -21,6 +21,10 @@
 # CHECK: encoding: [0x73,0x00,0x20,0x30]
 mret
 
+# CHECK-INST: dret
+# CHECK: encoding: [0x73,0x00,0x20,0x7b]
+dret
+
 # CHECK-INST: wfi
 # CHECK: encoding: [0x73,0x00,0x50,0x10]
 wfi
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -573,6 +573,12 @@
   let rs1 = 0;
   let rs2 = 0b00010;
 }
+
+def DRET : Priv<"dret", 0b0111101>, Sched<[]> {
+  let rd = 0;
+  let rs1 = 0;
+  let rs2 = 0b10010;
+}
 } // isBarrier = 1, isReturn = 1, isTerminator = 1
 
 def WFI : Priv<"wfi", 0b0001000>, Sched<[]> {


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