[llvm] 43abef0 - [PowerPC][Future] Initial support for PCRel addressing for jump tables.
Kamau Bridgeman via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 22 08:45:33 PDT 2020
Author: Victor Huang
Date: 2020-04-22T10:45:01-05:00
New Revision: 43abef06f42d5f9bab4e8363207d5c486705f6b6
URL: https://github.com/llvm/llvm-project/commit/43abef06f42d5f9bab4e8363207d5c486705f6b6
DIFF: https://github.com/llvm/llvm-project/commit/43abef06f42d5f9bab4e8363207d5c486705f6b6.diff
LOG: [PowerPC][Future] Initial support for PCRel addressing for jump tables.
Add initial support for PC Relative addressing to get jump table base
address instead of using TOC.
Differential Revision: https://reviews.llvm.org/D75931
Added:
llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll
Modified:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 3c3a144a9b98..4f065dfd4f7c 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2602,6 +2602,9 @@ bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const {
if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(N))
if (GAN->getTargetFlags() & PPCII::MO_PCREL_FLAG)
return true;
+ if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(N))
+ if (JT->getTargetFlags() & PPCII::MO_PCREL_FLAG)
+ return true;
return false;
}
@@ -2894,6 +2897,16 @@ SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
EVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
+ // isUsingPCRelativeCalls() returns true when PCRelative is enabled
+ if (Subtarget.isUsingPCRelativeCalls()) {
+ SDLoc DL(JT);
+ EVT Ty = getPointerTy(DAG.getDataLayout());
+ SDValue GA =
+ DAG.getTargetJumpTable(JT->getIndex(), Ty, PPCII::MO_PCREL_FLAG);
+ SDValue MatAddr = DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, GA);
+ return MatAddr;
+ }
+
// 64-bit SVR4 ABI and AIX ABI code are always position-independent.
// The actual address of the GlobalValue is stored in the TOC.
if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll b/llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll
new file mode 100644
index 000000000000..a7d3ca7e6d73
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/pcrel-jump-table.ll
@@ -0,0 +1,57 @@
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN: --check-prefix=CHECK-R
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=future -ppc-use-absolute-jumptables \
+; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s \
+; RUN: --check-prefix=CHECK-A
+
+; This test checks for getting relative and absolute jump table base address
+; using PC Relative addressing.
+
+define dso_local signext i32 @jumptable(i32 signext %param) {
+; CHECK-R-LABEL: jumptable:
+; CHECK-R: # %bb.1: # %entry
+; CHECK-R-NEXT: rldic r4, r4
+; CHECK-R-NEXT: paddi r5, 0, .LJTI0_0 at PCREL, 1
+; CHECK-R-NEXT: lwax r4, r4, r5
+; CHECK-R-NEXT: add r4, r4, r5
+; CHECK-R-NEXT: mtctr r4
+; CHECK-R-NEXT: bctr
+; CHECK-A-LABEL: jumptable:
+; CHECK-A: # %bb.1: # %entry
+; CHECK-A-NEXT: rldic r4, r4
+; CHECK-A-NEXT: paddi r5, 0, .LJTI0_0 at PCREL, 1
+; CHECK-A-NEXT: ldx r4, r4, r5
+; CHECK-A-NEXT: mtctr r4
+; CHECK-A-NEXT: bctr
+
+entry:
+ switch i32 %param, label %sw.default [
+ i32 1, label %return
+ i32 2, label %sw.bb1
+ i32 3, label %sw.bb2
+ i32 4, label %sw.bb3
+ i32 20, label %sw.bb4
+ ]
+
+sw.bb1: ; preds = %entry
+ br label %return
+
+sw.bb2: ; preds = %entry
+ br label %return
+
+sw.bb3: ; preds = %entry
+ br label %return
+
+sw.bb4: ; preds = %entry
+ br label %return
+
+sw.default: ; preds = %entry
+ br label %return
+
+return: ; preds = %entry, %sw.default, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1
+ %retval.0 = phi i32 [ -1, %sw.default ], [ 400, %sw.bb4 ], [ 16, %sw.bb3 ],
+ [ 9, %sw.bb2 ], [ 4, %sw.bb1 ], [ %param, %entry ]
+ ret i32 %retval.0
+}
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