[PATCH] D78468: [VE] Update shift operation instructions

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 marked an inline comment as done.
kaz7 added inline comments.


================
Comment at: llvm/lib/Target/VE/VEInstrInfo.td:1083
 
 // TODO Use standard expansion for shift-based lowering of sext_inreg
 
----------------
simoll wrote:
> Couldn't we just use LLVM's expansion legalizer for sext_inreg instead of specifying a pattern here? If not, then this comment should be removed.
Thank you for comments.  Using LLVM's expansion legalizer generates not optimized instructions sometimes.  For example, `%2 = trunc i64 %0 to i8` becomes following instructions:
```
        adds.w.sx %s0, %s0, (0)1
        sla.w.sx %s0, %s0, 24
        sra.w.sx %s0, %s0, 24
```
instead of instructions generated by current patterns:
```
        sll %s0, %s0, 56
        sra.l %s0, %s0, 56
```
It may be possible to expand them based on 64 bit registers using default legalizer, but I'm not sure how to do that.


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