[PATCH] D78174: [VE] Add alternative names to registers

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 marked 2 inline comments as done.
kaz7 added a comment.





================
Comment at: llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp:39
 void VEInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
-  OS << '%' << StringRef(getRegisterName(RegNo)).lower();
+  // Generic registers have identical regitster name among register classes.
+  unsigned AltIdx = VE::AsmName;
----------------
arsenm wrote:
> Typo regitster
Thank you.  Corrected it.


================
Comment at: llvm/lib/Target/VE/VERegisterInfo.td:39
 foreach I = 0-63 in
-  def SB#I : R<I, "S"#I>, DwarfRegNum<[I]>;
+  def SB#I : VEReg<I, "SB"#I, [], ["S"#I]>, DwarfRegNum<[I]>;
 
----------------
arsenm wrote:
> You can just lower case the original names unless you want to handle printing both capital and upper case for some reason
Thanks.  Changed to use lower case in string representations.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78174/new/

https://reviews.llvm.org/D78174