[PATCH] D78174: [VE] Add alternative names to registers

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp:39
 void VEInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
-  OS << '%' << StringRef(getRegisterName(RegNo)).lower();
+  // Generic registers have identical regitster name among register classes.
+  unsigned AltIdx = VE::AsmName;
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Typo regitster


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Comment at: llvm/lib/Target/VE/VERegisterInfo.td:39
 foreach I = 0-63 in
-  def SB#I : R<I, "S"#I>, DwarfRegNum<[I]>;
+  def SB#I : VEReg<I, "SB"#I, [], ["S"#I]>, DwarfRegNum<[I]>;
 
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You can just lower case the original names unless you want to handle printing both capital and upper case for some reason


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78174/new/

https://reviews.llvm.org/D78174