[PATCH] D77564: [PowerPC] Do not attempt to reuse load for 64-bit FP_TO_UINT without FPCVT

[Nemanja Ivanovic via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG64b31d96dfd6: [PowerPC] Do not attempt to reuse load for 64-bit FP_TO_UINT without FPCVT (authored by nemanjai).

Changed prior to commit:
  https://reviews.llvm.org/D77564?vs=255366&id=258801#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77564/new/

https://reviews.llvm.org/D77564

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/pr43976.ll


Index: llvm/test/CodeGen/PowerPC/pr43976.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/pr43976.ll
@@ -0,0 +1,59 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64-unknown-unknown -verify-machineinstrs \
+; RUN:   -ppc-asm-full-reg-names < %s | FileCheck %s
+ at a = dso_local local_unnamed_addr global double 0.000000e+00, align 8
+
+define dso_local signext i32 @b() local_unnamed_addr #0 {
+; CHECK-LABEL: b:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr r0
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stdu r1, -144(r1)
+; CHECK-NEXT:    addis r3, r2, a at toc@ha
+; CHECK-NEXT:    addis r4, r2, .LCPI0_0 at toc@ha
+; CHECK-NEXT:    lfd f0, a at toc@l(r3)
+; CHECK-NEXT:    lfs f1, .LCPI0_0 at toc@l(r4)
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    sldi r4, r4, 63
+; CHECK-NEXT:    fsub f2, f0, f1
+; CHECK-NEXT:    fctidz f2, f2
+; CHECK-NEXT:    stfd f2, 128(r1)
+; CHECK-NEXT:    fctidz f2, f0
+; CHECK-NEXT:    stfd f2, 120(r1)
+; CHECK-NEXT:    ld r3, 128(r1)
+; CHECK-NEXT:    ld r5, 120(r1)
+; CHECK-NEXT:    fcmpu cr0, f0, f1
+; CHECK-NEXT:    xor r3, r3, r4
+; CHECK-NEXT:    bc 12, lt, .LBB0_1
+; CHECK-NEXT:    b .LBB0_2
+; CHECK-NEXT:  .LBB0_1: # %entry
+; CHECK-NEXT:    addi r3, r5, 0
+; CHECK-NEXT:  .LBB0_2: # %entry
+; CHECK-NEXT:    std r3, 112(r1)
+; CHECK-NEXT:    addis r3, r2, .LCPI0_1 at toc@ha
+; CHECK-NEXT:    lfd f0, 112(r1)
+; CHECK-NEXT:    lfs f1, .LCPI0_1 at toc@l(r3)
+; CHECK-NEXT:    fcfid f0, f0
+; CHECK-NEXT:    fmul f0, f0, f1
+; CHECK-NEXT:    fctiwz f0, f0
+; CHECK-NEXT:    stfd f0, 136(r1)
+; CHECK-NEXT:    lwa r3, 140(r1)
+; CHECK-NEXT:    bl g
+; CHECK-NEXT:    nop
+; CHECK-NEXT:    addi r1, r1, 144
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    mtlr r0
+; CHECK-NEXT:    blr
+entry:
+  %0 = load double, double* @a, align 8
+  %conv = fptoui double %0 to i64
+  %conv1 = sitofp i64 %conv to double
+  %mul = fmul double %conv1, 1.000000e+06
+  %conv2 = fptosi double %mul to i32
+  %call = tail call signext i32 @g(i32 signext %conv2) #0
+  ret i32 %call
+}
+
+declare signext i32 @g(i32 signext) local_unnamed_addr
+
+attributes #0 = { nounwind }
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8210,9 +8210,10 @@
                                             SelectionDAG &DAG,
                                             ISD::LoadExtType ET) const {
   SDLoc dl(Op);
+  bool ValidFPToUint = Op.getOpcode() == ISD::FP_TO_UINT &&
+                       (Subtarget.hasFPCVT() || Op.getValueType() == MVT::i32);
   if (ET == ISD::NON_EXTLOAD &&
-      (Op.getOpcode() == ISD::FP_TO_UINT ||
-       Op.getOpcode() == ISD::FP_TO_SINT) &&
+      (ValidFPToUint || Op.getOpcode() == ISD::FP_TO_SINT) &&
       isOperationLegalOrCustom(Op.getOpcode(),
                                Op.getOperand(0).getValueType())) {
 


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