[PATCH] D78364: [MC][Bugfix] Remove redundant parameter for relaxInstruction

[Luís Marques via Phabricator via llvm-commits]

luismarques marked an inline comment as done.
luismarques added inline comments.


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Comment at: llvm/test/MC/RISCV/rv64-relax-all.s:9-11
+# INSTR:           c.beqz    a0, 0 <NEAR>
+# RELAX-INSTR:     beq    a0, zero, 0 <NEAR>
+c.beqz a0, NEAR
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luismarques wrote:
> I'm confused about this. When you relax the instruction it goes from a compressed instruction to an uncompressed one?
Ah, I see which patch this came from. When I think of RISC-V relaxations I associate with going from the more general code pattern to the more restricted one, such as the ones requested by RISC-V relaxation relocations, so I was surprised by this.


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https://reviews.llvm.org/D78364