[PATCH] D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill updated this revision to Diff 258112.
lewis-revill added a comment.

Add testing for shifts. Include a version of handling single word operations on RV64 involving directly lowering to the final opcode.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76354/new/

https://reviews.llvm.org/D76354

Files:
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/Target/RISCV/RISCVLegalizerInfo.cpp
  llvm/lib/Target/RISCV/RISCVLegalizerInfo.h
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/alu32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/alu64.mir

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