[PATCH] D76354: [WIP][RISCV][GlobalISel] Legalize types for ALU operations

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVLegalizerInfo.cpp:105
+  // TODO: We have better patterns for this depending on the operand.
+  getActionDefinitionsBuilder(G_SEXT_INREG).lower();
+
----------------
Currently RISC-V defines signext_inreg as legal when we know that the inner type is i32. However with GlobalISel there is no way to retrieve the inner type to define legality, as the action of G_SEXT_INREG is determined by an immediate operand.

I was currently in the process of rewriting these patches to properly handle single word operations on RV64, of which ADDW, SUBW and MULW rely on pattern matching an i32 to i64 signext_inreg of the corresponding operation. Though since we cannot allow the G_SEXT_INREG to survive correctly I feel the only option for now may be to directly select these instructions at the legalization stage.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76354/new/

https://reviews.llvm.org/D76354