[PATCH] D78272: [PowerPC] DAG Combine to transform shifts into multiply-high

[Amy Kwan via Phabricator via llvm-commits]

amyk created this revision.
amyk added reviewers: PowerPC, power-llvm-team, nemanjai, stefanp, hfinkel.
Herald added subscribers: llvm-commits, shchenz, kbarton, hiraditya.
Herald added a project: LLVM.

This patch implements a custom combine to produce the 32-bit and 64-bit
multiply-high instructions from shifts. It focuses on catching the patterns:

  (shift (mul (ext i32:$a to i64), (ext i32:$b to i64)), 32)
  (shift (mul (ext i64:$a to i128), (ext i64:$b to i128)), 64)

to produce `mulhs` when we have a sign-extend, and `mulhu` when we have
a zero-extend.

**The patch performs the following checks:**

- Operation is a right shift arithmetic (`sra`) or logical (`srl`)
- Input to the shift is a multiply
- Both operands to the shift are sext/zext nodes
- The extends into the multiply are both the same
- The narrow type is half the width of the wide type
- The shift amount is the width of the narrow type
- The respective mulh operation is legal


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78272

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/combine-to-mulh-shift-amount.ll
  llvm/test/CodeGen/PowerPC/mul-high.ll

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