[llvm] 322ac2e - [X86][MC][NFC] Reduce the parameters of functions in X86MCCodeEmitter(Part I)
Shengchen Kan via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 15 18:54:28 PDT 2020
Author: Shengchen Kan
Date: 2020-04-16T09:53:45+08:00
New Revision: 322ac2e9173a6fc778f10cf528c676c9159d893f
URL: https://github.com/llvm/llvm-project/commit/322ac2e9173a6fc778f10cf528c676c9159d893f
DIFF: https://github.com/llvm/llvm-project/commit/322ac2e9173a6fc778f10cf528c676c9159d893f.diff
LOG: [X86][MC][NFC] Reduce the parameters of functions in X86MCCodeEmitter(Part I)
Summary:
The function in X86MCCodeEmitter has too many parameters to make it look
messy, and some parameters are unnecessary. This is the first patch to
reduce their parameters.
The follwing operations are cheap
```
unsigned Opcode = MI.getOpcode();
const MCInstrDesc &Desc = MCII.get(Opcode);
uint64_t TSFlags = Desc.TSFlags;
```
So if we pass a `MCInst`, we don't need to pass `MCInstrDesc`;
if we pass a `MCInstrDesc`, we don't need to pass `TSFlags`.
Reviewers: craig.topper, MaskRay, pengfei
Reviewed By: craig.topper
Subscribers: annita.zhang, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78180
Added:
Modified:
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 357599b0e13a..43e31e05518b 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -111,23 +111,20 @@ class X86MCCodeEmitter : public MCCodeEmitter {
raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
- void emitPrefixImpl(uint64_t TSFlags, unsigned &CurOp, unsigned &CurByte,
- bool &Rex, const MCInst &MI, const MCInstrDesc &Desc,
- const MCSubtargetInfo &STI, raw_ostream &OS) const;
+ void emitPrefixImpl(unsigned &CurOp, unsigned &CurByte, bool &Rex,
+ const MCInst &MI, const MCSubtargetInfo &STI,
+ raw_ostream &OS) const;
- void emitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
- const MCInst &MI, const MCInstrDesc &Desc,
+ void emitVEXOpcodePrefix(unsigned &CurByte, int MemOperand, const MCInst &MI,
raw_ostream &OS) const;
void emitSegmentOverridePrefix(unsigned &CurByte, unsigned SegOperand,
const MCInst &MI, raw_ostream &OS) const;
- bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
- const MCInst &MI, const MCInstrDesc &Desc,
+ bool emitOpcodePrefix(unsigned &CurByte, int MemOperand, const MCInst &MI,
const MCSubtargetInfo &STI, raw_ostream &OS) const;
- uint8_t determineREXPrefix(const MCInst &MI, uint64_t TSFlags, int MemOperand,
- const MCInstrDesc &Desc) const;
+ uint8_t determineREXPrefix(const MCInst &MI, int MemOperand) const;
};
} // end anonymous namespace
@@ -633,11 +630,11 @@ void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op,
CurByte, OS, Fixups);
}
-void X86MCCodeEmitter::emitPrefixImpl(uint64_t TSFlags, unsigned &CurOp,
- unsigned &CurByte, bool &Rex,
- const MCInst &MI, const MCInstrDesc &Desc,
- const MCSubtargetInfo &STI,
- raw_ostream &OS) const {
+void X86MCCodeEmitter::emitPrefixImpl(unsigned &CurOp, unsigned &CurByte,
+ bool &Rex, const MCInst &MI,
+ const MCSubtargetInfo &STI,
+ raw_ostream &OS) const {
+ uint64_t TSFlags = MCII.get(MI.getOpcode()).TSFlags;
// Determine where the memory operand starts, if present.
int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
if (MemoryOperand != -1)
@@ -682,9 +679,9 @@ void X86MCCodeEmitter::emitPrefixImpl(uint64_t TSFlags, unsigned &CurOp,
// Encoding type for this instruction.
uint64_t Encoding = TSFlags & X86II::EncodingMask;
if (Encoding == 0)
- Rex = emitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, STI, OS);
+ Rex = emitOpcodePrefix(CurByte, MemoryOperand, MI, STI, OS);
else
- emitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
+ emitVEXOpcodePrefix(CurByte, MemoryOperand, MI, OS);
uint64_t Form = TSFlags & X86II::FormMask;
switch (Form) {
@@ -737,10 +734,12 @@ void X86MCCodeEmitter::emitPrefixImpl(uint64_t TSFlags, unsigned &CurOp,
/// emitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
/// called VEX.
-void X86MCCodeEmitter::emitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
- int MemOperand, const MCInst &MI,
- const MCInstrDesc &Desc,
+void X86MCCodeEmitter::emitVEXOpcodePrefix(unsigned &CurByte, int MemOperand,
+ const MCInst &MI,
raw_ostream &OS) const {
+ const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
+ uint64_t TSFlags = Desc.TSFlags;
+
assert(!(TSFlags & X86II::LOCK) && "Can't have LOCK VEX.");
uint64_t Encoding = TSFlags & X86II::EncodingMask;
@@ -1168,12 +1167,14 @@ void X86MCCodeEmitter::emitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
/// Determine if the MCInst has to be encoded with a X86-64 REX prefix which
/// specifies 1) 64-bit instructions, 2) non-default operand size, and 3) use
/// of X86-64 extended registers.
-uint8_t X86MCCodeEmitter::determineREXPrefix(const MCInst &MI, uint64_t TSFlags,
- int MemOperand,
- const MCInstrDesc &Desc) const {
+uint8_t X86MCCodeEmitter::determineREXPrefix(const MCInst &MI,
+ int MemOperand) const {
uint8_t REX = 0;
bool UsesHighByteReg = false;
+ const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
+ uint64_t TSFlags = Desc.TSFlags;
+
if (TSFlags & X86II::REX_W)
REX |= 1 << 3; // set REX.W
@@ -1272,11 +1273,13 @@ void X86MCCodeEmitter::emitSegmentOverridePrefix(unsigned &CurByte,
/// If not present, it is -1.
///
/// \returns true if a REX prefix was used.
-bool X86MCCodeEmitter::emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
- int MemOperand, const MCInst &MI,
- const MCInstrDesc &Desc,
+bool X86MCCodeEmitter::emitOpcodePrefix(unsigned &CurByte, int MemOperand,
+ const MCInst &MI,
const MCSubtargetInfo &STI,
raw_ostream &OS) const {
+ const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
+ uint64_t TSFlags = Desc.TSFlags;
+
bool Ret = false;
// Emit the operand size opcode prefix as needed.
if ((TSFlags & X86II::OpSizeMask) ==
@@ -1306,7 +1309,7 @@ bool X86MCCodeEmitter::emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
// Handle REX prefix.
// FIXME: Can this come before F2 etc to simplify emission?
if (STI.hasFeature(X86::Mode64Bit)) {
- if (uint8_t REX = determineREXPrefix(MI, TSFlags, MemOperand, Desc)) {
+ if (uint8_t REX = determineREXPrefix(MI, MemOperand)) {
emitByte(0x40 | REX, CurByte, OS);
Ret = true;
}
@@ -1351,7 +1354,7 @@ void X86MCCodeEmitter::emitPrefix(const MCInst &MI, raw_ostream &OS,
unsigned CurByte = 0;
bool Rex = false;
- emitPrefixImpl(TSFlags, CurOp, CurByte, Rex, MI, Desc, STI, OS);
+ emitPrefixImpl(CurOp, CurByte, Rex, MI, STI, OS);
}
void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
@@ -1372,7 +1375,7 @@ void X86MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
unsigned CurByte = 0;
bool Rex = false;
- emitPrefixImpl(TSFlags, CurOp, CurByte, Rex, MI, Desc, STI, OS);
+ emitPrefixImpl(CurOp, CurByte, Rex, MI, STI, OS);
// It uses the VEX.VVVV field?
bool HasVEX_4V = TSFlags & X86II::VEX_4V;
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