[PATCH] D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

You need to add tests for selection and moveToVALU, including immediates and wave32.



================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp:1087
+    for (auto Use : N->uses()) {
+      if (Use->isMachineOpcode() && TII->isVALU(Use->getMachineOpcode())) {
+        IsVALU = true;
----------------
Should it look thru PHI and COPY? It may need a helper function though.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:3700
+    const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
+    const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
+    const TargetRegisterClass *Src0SubRC =
----------------
It can me immediate, maybe even a FI.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:3765
+    }
+    if (TRI->isVectorRegister(MRI, Src1.getReg())) {
+      Register RegOp1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
----------------
Same here, it can be an immediate, right?


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:5202
+    }
+      continue;
+    case AMDGPU::S_UADDO_PSEUDO:
----------------
Formatting is off.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:5236
+    }
+      continue;
     }
----------------
Formatting is off.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:5981
+        for (auto &U : Users)
+          U->getOperand(4).setReg(AMDGPU::VCC);
+        CopyToDelete.push_back(&MI);
----------------
VCC_LO for wave32?


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  https://reviews.llvm.org/D78091/new/

https://reviews.llvm.org/D78091