[PATCH] D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp:1086
+  if (!IsVALU) {
+    for (auto Use : N->uses()) {
+      if (Use->isMachineOpcode() && TII->isVALU(Use->getMachineOpcode())) {
----------------
Shouldn't need to scan all uses?


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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:3618-3621
+    if (Src1.isReg())
+      CarryOp.addReg(Src1.getReg());
+    else if (Src1.isImm())
+      CarryOp.addImm(Src1.getImm());
----------------
This ignores other things it could be. You can just use .add()


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:3623-3625
+    BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CSELECT_B64), Dest1.getReg())
+        .addImm(1)
+        .addImm(0);
----------------
You can just do COPY from SCC


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78091/new/

https://reviews.llvm.org/D78091