[PATCH] D77387: [ARM] Fix conditions for lowering to S[LR]I

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Thanks. LGTM.



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:3153-3157
+    ConstantSDNode *CShiftNode = dyn_cast<ConstantSDNode>(Op.getOperand(3));
+    if (!CShiftNode)
+      report_fatal_error("Shift amount must be constant for aarch64_neon_vsli");
+
+    uint64_t ShiftAmount = CShiftNode->getZExtValue();
----------------
You could possibly use uint64_t ShiftAmount = Op.getConstantOperandVal(3), simplify it a little. It won't handle the report_fatal_error, but this should have already been checked at a higher level, somewhere in clang to make sure the shift amount is a constant.

Same for the ElemSizeInBits check below. You could change them to asserts. Up to you.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77387/new/

https://reviews.llvm.org/D77387