[PATCH] D77895: [x86] use vector instructions to lower FP->int->FP casts

[Peter Cordes via Phabricator via llvm-commits]

pcordes added a comment.

Looks good to me, too.  SSE4.1 still uses roundss which is at least as good.  (1 uop on SnB and AMD, 2 uops on HSW/SKL).

While we're looking at this, could we use `[v]roundss $11, src, src, dst` when available for no-fast-math?

float->int overflow is UB so ISO C allows us to assume it doesn't happen.  Unless we want to go beyond that, we don't need to preserve the behaviour of producing `0x80000000` as an integer result from the overflowing `(int)` cast and then converting that back to a float that represents that negative value, for out-of-range inputs.  But if this optimization stage happens late enough on IR that does expect those semantics, that's different.  But behaviour for similar asm instructions on other ISAs might not give the same bit-pattern so I'm not sure how useful this is.  e.g. ARM conversions saturate to the bounds of the int value-range.

(I meant to just mark my review as "looks good to me", but I think that actually marked it as officially accepted.  Let me know if that wasn't what the preferred course of action.)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77895/new/

https://reviews.llvm.org/D77895