[PATCH] D65649: [RISCV] Add MC encodings and tests of the Bit Manipulation extension

[Simon Cook via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGfae40bd5a1d4: [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0. (authored by PaoloS, committed by simoncook).

Changed prior to commit:
  https://reviews.llvm.org/D65649?vs=253455&id=256368#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65649/new/

https://reviews.llvm.org/D65649

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/MC/RISCV/compress-rv32b.s
  llvm/test/MC/RISCV/compress-rv64b.s
  llvm/test/MC/RISCV/rv32b-aliases-valid.s
  llvm/test/MC/RISCV/rv32zbb-invalid.s
  llvm/test/MC/RISCV/rv32zbb-valid.s
  llvm/test/MC/RISCV/rv32zbbp-invalid.s
  llvm/test/MC/RISCV/rv32zbbp-valid.s
  llvm/test/MC/RISCV/rv32zbc-invalid.s
  llvm/test/MC/RISCV/rv32zbc-valid.s
  llvm/test/MC/RISCV/rv32zbe-invalid.s
  llvm/test/MC/RISCV/rv32zbe-valid.s
  llvm/test/MC/RISCV/rv32zbf-invalid.s
  llvm/test/MC/RISCV/rv32zbf-valid.s
  llvm/test/MC/RISCV/rv32zbp-invalid.s
  llvm/test/MC/RISCV/rv32zbp-valid.s
  llvm/test/MC/RISCV/rv32zbproposedc-invalid.s
  llvm/test/MC/RISCV/rv32zbproposedc-valid.s
  llvm/test/MC/RISCV/rv32zbr-invalid.s
  llvm/test/MC/RISCV/rv32zbr-valid.s
  llvm/test/MC/RISCV/rv32zbs-invalid.s
  llvm/test/MC/RISCV/rv32zbs-valid.s
  llvm/test/MC/RISCV/rv32zbt-invalid.s
  llvm/test/MC/RISCV/rv32zbt-valid.s
  llvm/test/MC/RISCV/rv64b-aliases-valid.s
  llvm/test/MC/RISCV/rv64zbb-invalid.s
  llvm/test/MC/RISCV/rv64zbb-valid.s
  llvm/test/MC/RISCV/rv64zbbp-invalid.s
  llvm/test/MC/RISCV/rv64zbbp-valid.s
  llvm/test/MC/RISCV/rv64zbc-invalid.s
  llvm/test/MC/RISCV/rv64zbc-valid.s
  llvm/test/MC/RISCV/rv64zbe-invalid.s
  llvm/test/MC/RISCV/rv64zbe-valid.s
  llvm/test/MC/RISCV/rv64zbf-invalid.s
  llvm/test/MC/RISCV/rv64zbf-valid.s
  llvm/test/MC/RISCV/rv64zbm-invalid.s
  llvm/test/MC/RISCV/rv64zbm-valid.s
  llvm/test/MC/RISCV/rv64zbp-invalid.s
  llvm/test/MC/RISCV/rv64zbp-valid.s
  llvm/test/MC/RISCV/rv64zbproposedc-invalid.s
  llvm/test/MC/RISCV/rv64zbproposedc-valid.s
  llvm/test/MC/RISCV/rv64zbr-invalid.s
  llvm/test/MC/RISCV/rv64zbr-valid.s
  llvm/test/MC/RISCV/rv64zbs-invalid.s
  llvm/test/MC/RISCV/rv64zbs-valid.s
  llvm/test/MC/RISCV/rv64zbt-invalid.s
  llvm/test/MC/RISCV/rv64zbt-valid.s

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