[llvm] ca0ace7 - CodeGen: Use Register in MachineBasicBlock
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Wed Apr 8 09:11:12 PDT 2020
Author: Matt Arsenault
Date: 2020-04-08T12:10:58-04:00
New Revision: ca0ace72987eb776f3103cf444bd160094a50cbc
URL: https://github.com/llvm/llvm-project/commit/ca0ace72987eb776f3103cf444bd160094a50cbc
DIFF: https://github.com/llvm/llvm-project/commit/ca0ace72987eb776f3103cf444bd160094a50cbc.diff
LOG: CodeGen: Use Register in MachineBasicBlock
Added:
Modified:
llvm/include/llvm/CodeGen/LiveIntervals.h
llvm/include/llvm/CodeGen/MachineBasicBlock.h
llvm/lib/CodeGen/LiveIntervals.cpp
llvm/lib/CodeGen/MachineBasicBlock.cpp
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/LiveIntervals.h b/llvm/include/llvm/CodeGen/LiveIntervals.h
index 2bfc99624937..386fa2cd47eb 100644
--- a/llvm/include/llvm/CodeGen/LiveIntervals.h
+++ b/llvm/include/llvm/CodeGen/LiveIntervals.h
@@ -333,7 +333,7 @@ class VirtRegMap;
void repairIntervalsInRange(MachineBasicBlock *MBB,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
- ArrayRef<unsigned> OrigRegs);
+ ArrayRef<Register> OrigRegs);
// Register mask functions.
//
diff --git a/llvm/include/llvm/CodeGen/MachineBasicBlock.h b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
index cd33a3714908..e8dabc3eef39 100644
--- a/llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ b/llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -357,7 +357,7 @@ class MachineBasicBlock
/// Add PhysReg as live in to this block, and ensure that there is a copy of
/// PhysReg to a virtual register of class RC. Return the virtual register
/// that is a copy of the live in PhysReg.
- unsigned addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC);
+ Register addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC);
/// Remove the specified register from the live in set.
void removeLiveIn(MCPhysReg Reg,
@@ -854,7 +854,7 @@ class MachineBasicBlock
///
/// \p Reg must be a physical register.
LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI,
- unsigned Reg,
+ MCRegister Reg,
const_iterator Before,
unsigned Neighborhood = 10) const;
diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index 9c80282bc59e..1b427e00b075 100644
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -1587,7 +1587,7 @@ void
LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
- ArrayRef<unsigned> OrigRegs) {
+ ArrayRef<Register> OrigRegs) {
// Find anchor points, which are at the beginning/end of blocks or at
// instructions that already have indexes.
while (Begin != MBB->begin() && !Indexes->hasIndex(*Begin))
@@ -1618,8 +1618,8 @@ LiveIntervals::repairIntervalsInRange(MachineBasicBlock *MBB,
}
}
- for (unsigned Reg : OrigRegs) {
- if (!Register::isVirtualRegister(Reg))
+ for (Register Reg : OrigRegs) {
+ if (!Reg.isVirtual())
continue;
LiveInterval &LI = getInterval(Reg);
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index b273da862fa3..3fa60dd45aa2 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -498,7 +498,7 @@ void MachineBasicBlock::sortUniqueLiveIns() {
LiveInVector::const_iterator J;
LiveInVector::iterator Out = LiveIns.begin();
for (; I != LiveIns.end(); ++Out, I = J) {
- unsigned PhysReg = I->PhysReg;
+ MCRegister PhysReg = I->PhysReg;
LaneBitmask LaneMask = I->LaneMask;
for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
LaneMask |= J->LaneMask;
@@ -508,7 +508,7 @@ void MachineBasicBlock::sortUniqueLiveIns() {
LiveIns.erase(Out, LiveIns.end());
}
-unsigned
+Register
MachineBasicBlock::addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC) {
assert(getParent() && "MBB must be inserted in function");
assert(PhysReg.isPhysical() && "Expected physreg");
@@ -960,7 +960,7 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
LiveVariables *LV = P.getAnalysisIfAvailable<LiveVariables>();
// Collect a list of virtual registers killed by the terminators.
- SmallVector<unsigned, 4> KilledRegs;
+ SmallVector<Register, 4> KilledRegs;
if (LV)
for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
I != E; ++I) {
@@ -980,7 +980,7 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
}
}
- SmallVector<unsigned, 4> UsedRegs;
+ SmallVector<Register, 4> UsedRegs;
if (LIS) {
for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
I != E; ++I) {
@@ -1054,7 +1054,7 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
if (LV) {
// Restore kills of virtual registers that were killed by the terminators.
while (!KilledRegs.empty()) {
- unsigned Reg = KilledRegs.pop_back_val();
+ Register Reg = KilledRegs.pop_back_val();
for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
if (!(--I)->addRegisterKilled(Reg, TRI, /* AddIfNotFound= */ false))
continue;
@@ -1087,7 +1087,7 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);
// Find the registers used from NMBB in PHIs in Succ.
- SmallSet<unsigned, 8> PHISrcRegs;
+ SmallSet<Register, 8> PHISrcRegs;
for (MachineBasicBlock::instr_iterator
I = Succ->instr_begin(), E = Succ->instr_end();
I != E && I->isPHI(); ++I) {
@@ -1110,7 +1110,7 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
MachineRegisterInfo *MRI = &getParent()->getRegInfo();
for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
- unsigned Reg = Register::index2VirtReg(i);
+ Register Reg = Register::index2VirtReg(i);
if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
continue;
@@ -1452,7 +1452,7 @@ MachineBasicBlock::getProbabilityIterator(MachineBasicBlock::succ_iterator I) {
/// instructions after (searching just for defs) MI.
MachineBasicBlock::LivenessQueryResult
MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
- unsigned Reg, const_iterator Before,
+ MCRegister Reg, const_iterator Before,
unsigned Neighborhood) const {
unsigned N = Neighborhood;
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index 336077f297d2..463311a2094a 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1419,7 +1419,7 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi,
LV->addVirtualRegisterKilled(Reg, *NewMIs[1]);
}
- SmallVector<unsigned, 4> OrigRegs;
+ SmallVector<Register, 4> OrigRegs;
if (LIS) {
for (const MachineOperand &MO : MI.operands()) {
if (MO.isReg())
@@ -1802,7 +1802,7 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) {
llvm_unreachable(nullptr);
}
- SmallVector<unsigned, 4> OrigRegs;
+ SmallVector<Register, 4> OrigRegs;
if (LIS) {
OrigRegs.push_back(MI.getOperand(0).getReg());
for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2)
diff --git a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
index 17e1196eea59..4b809e0c8553 100644
--- a/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
@@ -78,9 +78,9 @@ namespace {
Register OutReg = MI.getOperand(0).getReg();
Register InReg = MI.getOperand(1).getReg();
DebugLoc DL = MI.getDebugLoc();
- unsigned GPR3 = Is64Bit ? PPC::X3 : PPC::R3;
+ Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3;
unsigned Opc1, Opc2;
- const unsigned OrigRegs[] = {OutReg, InReg, GPR3};
+ const Register OrigRegs[] = {OutReg, InReg, GPR3};
switch (MI.getOpcode()) {
default:
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