[PATCH] D77650: TableGen/GlobalISel: Fix constraining REG_SEQUENCE operands

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: dsanders, paquette, aemerson, aditya_nandakumar, kerbowa, foad.
Herald added subscribers: tpr, rovka, nhaehnle, wdng, jvesely.

This was hitting the default instruction constraint code which uses
the register classes in the instruction def, which REG_SEQUENCE does
not have.

      

Fixes not constraining the register class for AMDGPU fneg/fabs
patterns, which would fail when the use was another generic,
unconstrained instruction.

      

Another oddity I noticed is that the temporary registers are created
with an unnecessary, but incorrect 16-bit LLT but this shouldn't
matter.

I'm also still unclear why root and sub-instructions have to be
handled differently.


https://reviews.llvm.org/D77650

Files:
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
  llvm/test/TableGen/GlobalISelEmitterRegSequence.td
  llvm/utils/TableGen/GlobalISelEmitter.cpp

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