[PATCH] D77114: Handle exp2 with proper vectorization and lowering to SVML calls

Sat Apr 4 20:46:48 PDT 2020

hoyFB added a comment.

In D77114#1958974 <https://reviews.llvm.org/D77114#1958974>, @craig.topper wrote:

> In D77114#1958944 <https://reviews.llvm.org/D77114#1958944>, @hoyFB wrote:
>
> > In D77114#1958885 <https://reviews.llvm.org/D77114#1958885>, @craig.topper wrote:
> >
> > > Is there a publicly available SVML library that is usable with LLVM that uses these function names? The Intel library that comes with icc uses these names but uses a non-standard calling convention that LLVM doesn't implement. The other library I'm aware of is some SVML functions embedded in libgcc or libm(not sure which), but they don't use the same names as the Intel library as far as I know.
> >
> >
> > I'm not aware of a publicly available SVML library. We've been targeting the Intel one. By standard calling convention do you mean the x86_64 System V calling convention where vector parameters are passed through XMM0 to XMM7 and returned in XMM0 and XMM1?
>
>
> I guess it does sort of match the SystemV calling convention. The SVML library does treat some of the vector registers as callee saved which is different than SystemV. But if LLVM thinks they are all clobbered that probably doesn't cause an issue. There are masked versions for 512-bit that take the mask in a k-register which LLVM wouldn't know how to do.

That's a good point. That might be why the masked AVX 512 versions are not supported if you at the `VecFuncs.def` file.

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