[PATCH] D77387: [ARM] Fix conditions for lowering to S[LR]I

Fri Apr 3 07:30:09 PDT 2020

PetreTudor added inline comments.

================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7946
   unsigned Intrin =
       IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
   SDValue ResultSLI =
----------------
dmgreen wrote:
> I know you didn't write this part, but it's generally not a great idea to lower via intrinsics if it can be helped.
> 
> Can you add a ISel node, a lot like ARMISD::VSHLIMM, and plumb that through tablegen instead?
Sure! I will start working on this right away.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77387/new/

https://reviews.llvm.org/D77387