[PATCH] D77387: [ARM] Fix conditions for lowering to S[LR]I
Dave Green via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 3 06:57:41 PDT 2020
dmgreen added a reviewer: t.p.northover.
dmgreen added a comment.
Looks good.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7946
unsigned Intrin =
IsShiftRight ? Intrinsic::aarch64_neon_vsri : Intrinsic::aarch64_neon_vsli;
SDValue ResultSLI =
----------------
I know you didn't write this part, but it's generally not a great idea to lower via intrinsics if it can be helped.
Can you add a ISel node, a lot like ARMISD::VSHLIMM, and plumb that through tablegen instead?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D77387/new/
https://reviews.llvm.org/D77387
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