[PATCH] D75885: [AArch64] Allow logical immediates to have all-1 in top bits

[Fangrui Song via Phabricator via llvm-commits]

MaskRay added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:761
+    // Avoid left shift by 64 directly.
+    uint64_t Upper = UINT64_C(-1) << (sizeof(T) * 4) << (sizeof(T) * 4);
+    // Allow all-0 or all-1 in top bits to permit bitwise NOT.
----------------
sdesmalen wrote:
> Is this the same as:
> ```uint64_t Upper = UINT64_C(-1) << (sizeof(T) * 8);```
> ?
http://eel.is/c++draft//expr.shift

> The behavior is undefined if the right operand is negative, or greater than or equal to the width of the promoted left operand.

This avoids direct left shift by 64.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75885/new/

https://reviews.llvm.org/D75885