[PATCH] D75885: [AArch64] Allow logical immediates to have all-1 in top bits

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp:761
+    // Avoid left shift by 64 directly.
+    uint64_t Upper = UINT64_C(-1) << (sizeof(T) * 4) << (sizeof(T) * 4);
+    // Allow all-0 or all-1 in top bits to permit bitwise NOT.
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Is this the same as:
```uint64_t Upper = UINT64_C(-1) << (sizeof(T) * 8);```
?


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Comment at: llvm/test/MC/AArch64/SVE/mov.s:210
+/// FIXME
+// CHECK-INST: dupm z0.h, #0x7f00
+// CHECK-ENCODING: [0xc0,0x44,0xc0,0x05]
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Disassembling to `dupm z0.h, #0x7f00` makes sense here.

The mov alias is preferred when `SVEMoveMaskPreferred` is `true`. This instructino would splat 0x7f00 into each 16-bit lane of z0, resulting in `0x7f007f007f007f00`. For this input, `SVEMoveMaskPreferred` returns false, so `dupm` is the correct disassembly.

So I'd say the fixme can be removed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75885/new/

https://reviews.llvm.org/D75885