[PATCH] D77224: [POC][SVE] Allow fixed width vector types to live in ZPRs

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally updated this revision to Diff 254231.
cameron.mcinally added a comment.

Rebase to appease Harbormaster...


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77224/new/

https://reviews.llvm.org/D77224

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64CallingConvention.td
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-fixed-width-arith.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D77224.254231.patch
Type: text/x-patch
Size: 24398 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200401/47651ebd/attachment.bin>