[PATCH] D77224: [POC][SVE] Allow fixed width vector types to live in ZPRs

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally created this revision.
cameron.mcinally added reviewers: efriedma, rengolin, paulwalker-arm.
Herald added subscribers: llvm-commits, psnobl, rkruppe, hiraditya, tschuett.
Herald added a project: LLVM.

[DO NOT MERGE]

This is a very rough patch to allow fixed vector types to live in ZPRs. It could be extended in a bunch of ways, but is now just an intuition pump for handling fixed width vectors in the SVE backend.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D77224

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64CallingConvention.td
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-fixed-width-arith.ll

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