[PATCH] D77152: [SelectionDAG] Better legalization for FSHL and FSHR

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Thanks, I was just starting to do this



================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:1100-1101
+  // Amount has to be interpreted modulo the old bit width.
+  Amount =
+      DAG.getNode(ISD::UREM, DL, VT, Amount, DAG.getConstant(OldBits, DL, VT));
+
----------------
Should this maintain the special case for power of 2 (the GlobalISel version won't have the power of 2 urem combines for a while)


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:1104
+  unsigned Opcode = N->getOpcode();
+  if (Opcode == ISD::FSHR)
+    // Increase Amount to shift the result into the lower bits of the promoted
----------------
Braces


================
Comment at: llvm/test/CodeGen/X86/vector-fshr-128.ll:2813-2815
 ; X32-SSE-LABEL: splatconstant_funnnel_v2i64:
 ; X32-SSE:       # %bb.0:
+; X32-SSE-NEXT:    pxor %xmm3, %xmm3
----------------
Bad looking regression?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77152/new/

https://reviews.llvm.org/D77152