[PATCH] D77118: [PowerPC] Ignore implicit register operands for MCInst
Zhang Kang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Mar 31 00:31:03 PDT 2020
ZhangKang created this revision.
ZhangKang added reviewers: kbarton, hiraditya, nemanjai, jsji, steven.zhang, PowerPC.
ZhangKang added a project: LLVM.
Herald added subscribers: danielkiss, shchenz, wuzish, kristof.beyls, tpr, qcolombet.
For below case:
cat `bool-math.mir `
---
name: add_zext_cmp_mask_same_size_result
body: |
bb.0:
liveins: $x3
renamable $r3 = RLWINM killed renamable $r3, 0, 31, 31, implicit $x3
renamable $r3 = SUBFIC killed renamable $r3, 27, implicit-def dead $carry, implicit-def $x3
BLR8 implicit $lr8, implicit $rm, implicit killed $x3
...
Use below command to build it:
llc -start-after=ppc-early-ret bool-math.mir -o bool-math.s
Before this patch, we will get:
rlwinm 3, 3, 0, 31, 31
subfic 3, 3, 27
blr
Note that `rlwinm 3, 3, 0, 31, 31<--> clrlwi 3, 3, 31`. But the mir case use `implicit $x3` for `RLWINM` and PPC conserve the `implicit $x3` for MCInst, so above case won't use Extended Mnemonic.
-----------
When doing the conversion: `MachineInst -> MCInst`, we should ignore the implicit operands.
I have seen `ARM` & `AMDGPU` have ignored the implicit operands when converting `MachineInst -> MCInst`.
ARM
---
ARMMCInstLower.cpp
72 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
73 MCOperand &MCOp) {
74 switch (MO.getType()) {
75 default: llvm_unreachable("unknown operand type");
76 case MachineOperand::MO_Register:
77 // Ignore all implicit register operands.
78 if (MO.isImplicit())
79 return false;
80 assert(!MO.getSubReg() &
AMDGPU
------
AMDGPUMCInstLower.cpp
126 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
127 MCOperand &MCOp) const {
170 case MachineOperand::MO_RegisterMask:
171 // Regmasks are like implicit defs.
172 return false;
173 }
174 }
After this patch, we will get
clrlwi 3, 3, 31
subfic 3, 3, 27
blr
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D77118
Files:
llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir
llvm/test/CodeGen/PowerPC/VSX-XForm-Scalars.ll
llvm/test/CodeGen/PowerPC/atomics-regression.ll
llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
llvm/test/CodeGen/PowerPC/bool-math.ll
llvm/test/CodeGen/PowerPC/branch_coalesce.ll
llvm/test/CodeGen/PowerPC/bswap64.ll
llvm/test/CodeGen/PowerPC/build-vector-tests.ll
llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir
llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
llvm/test/CodeGen/PowerPC/crbits.ll
llvm/test/CodeGen/PowerPC/dform-adjust.ll
llvm/test/CodeGen/PowerPC/expand-isel.ll
llvm/test/CodeGen/PowerPC/extract-and-store.ll
llvm/test/CodeGen/PowerPC/f128-aggregates.ll
llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
llvm/test/CodeGen/PowerPC/funnel-shift.ll
llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll
llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll
llvm/test/CodeGen/PowerPC/load-and-splat.ll
llvm/test/CodeGen/PowerPC/load-v4i8-improved.ll
llvm/test/CodeGen/PowerPC/memcmp.ll
llvm/test/CodeGen/PowerPC/optcmp.ll
llvm/test/CodeGen/PowerPC/optimize-andiso.ll
llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll
llvm/test/CodeGen/PowerPC/popcnt-zext.ll
llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll
llvm/test/CodeGen/PowerPC/pr25080.ll
llvm/test/CodeGen/PowerPC/pr33093.ll
llvm/test/CodeGen/PowerPC/pr35688.ll
llvm/test/CodeGen/PowerPC/pr38087.ll
llvm/test/CodeGen/PowerPC/pre-inc-disable.ll
llvm/test/CodeGen/PowerPC/qpx-load-splat.ll
llvm/test/CodeGen/PowerPC/qpx-s-sel.ll
llvm/test/CodeGen/PowerPC/qpx-sel.ll
llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll
llvm/test/CodeGen/PowerPC/sat-add.ll
llvm/test/CodeGen/PowerPC/scalar_vector_test_1.ll
llvm/test/CodeGen/PowerPC/scalar_vector_test_2.ll
llvm/test/CodeGen/PowerPC/scalar_vector_test_3.ll
llvm/test/CodeGen/PowerPC/scalar_vector_test_4.ll
llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
llvm/test/CodeGen/PowerPC/select_const.ll
llvm/test/CodeGen/PowerPC/setcc-logic.ll
llvm/test/CodeGen/PowerPC/shift_mask.ll
llvm/test/CodeGen/PowerPC/signbit-shift.ll
llvm/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll
llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
llvm/test/CodeGen/PowerPC/spill_p9_setb.ll
llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll
llvm/test/CodeGen/PowerPC/stack-realign.ll
llvm/test/CodeGen/PowerPC/swaps-le-6.ll
llvm/test/CodeGen/PowerPC/testBitReverse.ll
llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll
llvm/test/CodeGen/PowerPC/testComparesi32leu.ll
llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll
llvm/test/CodeGen/PowerPC/testComparesigesll.ll
llvm/test/CodeGen/PowerPC/testComparesigeull.ll
llvm/test/CodeGen/PowerPC/testComparesigtsll.ll
llvm/test/CodeGen/PowerPC/testComparesilesll.ll
llvm/test/CodeGen/PowerPC/testComparesileull.ll
llvm/test/CodeGen/PowerPC/testComparesiltsll.ll
llvm/test/CodeGen/PowerPC/testComparesllgesll.ll
llvm/test/CodeGen/PowerPC/testComparesllgeull.ll
llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll
llvm/test/CodeGen/PowerPC/testCompareslllesll.ll
llvm/test/CodeGen/PowerPC/testComparesllleull.ll
llvm/test/CodeGen/PowerPC/testComparesllltsll.ll
llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll
llvm/test/CodeGen/PowerPC/trunc-srl-load.ll
llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll
llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll
llvm/test/CodeGen/PowerPC/vec-min-max.ll
llvm/test/CodeGen/PowerPC/vec-trunc.ll
llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll
llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll
llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll
llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll
llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll
llvm/test/CodeGen/PowerPC/vsx.ll
llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
llvm/test/CodeGen/PowerPC/xray-conditional-return.ll
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