[PATCH] D76901: [AArch64][SVE] Add support for boolean logic and fcmp.

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added inline comments.


================
Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:1369
   def : SVE_3_Op_Pat<nxv2i1, op, nxv2i1, nxv2i1, nxv2i1, !cast<Instruction>(NAME)>;
+  def : Pat<(nxv2i1 (op_nopred (nxv2i1 PPRAny:$Pn), (nxv2i1 PPRAny:$Pm))),
+            (!cast<Instruction>(NAME) (PTRUE_D 31), PPRAny:$Pn, PPRAny:$Pm)>;
----------------
efriedma wrote:
> sdesmalen wrote:
> > Do we want to create a `SVE_2_Op_<..>_Pat` or something for these? There will be other instructions where this would be useful as well.
> > 
> > nit: please reverse the order so it matches the patterns straight above it.
> I'm not sure what that would look like.  Are you proposing something like SVE_2_Op_PTRUE_H_Pat/SVE_2_Op_PTRUE_S_Pat/etc.?
There's something similar in D71712:

```
class SVE_2_Op_AllActive_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
                             ValueType vt2, Instruction inst, Instruction ptrue>
: Pat<(vtd (op vt1:$Op1, vt2:$Op2)),
      (inst (ptrue 31), $Op1, $Op2)>;
```

Seems like a good fit, but I'm not sure...


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D76901/new/

https://reviews.llvm.org/D76901